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AArch64 OPd_f and OPf_d conversions #20815

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Feb 3, 2025
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AArch64 OPd_f and OPf_d conversions #20815

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37 changes: 37 additions & 0 deletions compiler/src/dmd/backend/arm/cod4.d
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Original file line number Diff line number Diff line change
Expand Up @@ -1362,6 +1362,43 @@
fixresult(cdb,e,retregs,pretregs);
break;

case OPd_f: // fcvt d31,s31
case OPf_d: // fcvt s31,d31
regm_t retregs1 = ALLREGS; //INSTR.FLOATREGS;

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compiler/src/dmd/backend/arm/cod4.d#L1365-L1367 

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static if (1)
retregs1 = mCX; // hack because no floating support in rest of code

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compiler/src/dmd/backend/arm/cod4.d#L1369 

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else
codelem(cgstate,cdb,e.E1,retregs1,false);
const reg_t V1 = findreg(retregs1); // source floating point register

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static if (1)
{
regm_t retregs = mDX;

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compiler/src/dmd/backend/arm/cod4.d#L1376 

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}
else
{
regm_t retregs = pretregs & INSTR.FLOATREGS;
if (retregs == 0)
retregs = INSTR.FLOATREGS & cgstate.allregs;
}
const tym = tybasic(e.Ety);
reg_t Vd = allocreg(cdb,retregs,tym); // destination integer register

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switch (e.Eoper)

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compiler/src/dmd/backend/arm/cod4.d#L1387 

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{
case OPd_f: // fcvt s31,d31
cdb.gen1(INSTR.fcvt_float(1,4,V1,Vd));
break;
case OPf_d: // fcvt d31,s31
cdb.gen1(INSTR.fcvt_float(0,5,V1,Vd));
break;

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default:
assert(0);
}

fixresult(cdb,e,retregs,pretregs);
break;

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default:
assert(0);
}
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2 changes: 1 addition & 1 deletion compiler/src/dmd/backend/arm/disasmarm.d
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Expand Up @@ -1994,7 +1994,7 @@ void disassemble(uint c) @trusted
field(ins,21,21) == 1 &&
field(ins,14,10) == 0x10)
{
url = "floatdpl";
url = "floatdp1";

uint M = field(ins,31,31);
uint S = field(ins,29,29);
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6 changes: 5 additions & 1 deletion compiler/src/dmd/backend/arm/instr.d
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Expand Up @@ -718,9 +718,13 @@
static uint floatdp1(uint M, uint S, uint ftype, uint opcode, uint Rn, uint Rd)
{
assert(Rn < 32 && Rd < 32); // remember to convert R32-63 to 0-31
return (M << 31) | (S << 29) | (0x1E << 24) | (ftype << 22) | (1 << 21) | (0x10 << 10) | (Rn << 5) | Rd;
return (M << 31) | (S << 29) | (0x1E << 24) | (ftype << 22) | (1 << 21) | (opcode << 15) | (0x10 << 10) | (Rn << 5) | Rd;

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}

/* FCVT fpreg,fpreg https://www.scs.stanford.edu/~zyedidia/arm64/fcvt_float.html
*/
static uint fcvt_float(uint ftype, uint opcode, reg_t Rn, reg_t Rd) { return floatdp1(0,0,ftype,opcode,Rn,Rd); }

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/* Floating-point compare
* Floating-point immediate
* Floating-point condistional compare
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