mpu.c

/*
 * mpu.c
 *
 *  Created on: Mar 31, 2020
 *      Author: JaYniL~LM10
 */
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include "mpu.h"
#include "tm4c123gh6pm.h"

void MPU_init()
{
/*    NVIC_MPU_NUMBER_R = 0;
    NVIC_MPU_ATTR_R = (MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RW_USR_NO |SRAM_TEX_S_C_B_FULL
                | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_4G | MPU_RGN_ENABLE);*/
   /* NVIC_MPU_NUMBER_R = 0;
       NVIC_MPU_ATTR_R = ( MPU_RGN_PERM_NOEXEC | MPU_RGN_PERM_PRV_NO_USR_NO |FLASH_MEM_TEX_S_C_B
               | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_4G| MPU_RGN_ENABLE);*/

    NVIC_MPU_NUMBER_R = 1;
    NVIC_MPU_ATTR_R = ( MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |FLASH_MEM_TEX_S_C_B
            | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_256K| MPU_RGN_ENABLE);

    NVIC_MPU_NUMBER_R = 2;
    NVIC_MPU_BASE_R = PERIPH_BASE_ADD;
    NVIC_MPU_ATTR_R = ( MPU_RGN_PERM_NOEXEC | MPU_RGN_PERM_PRV_RW_USR_RW |PERIPHERAL_TEX_S_C_B
            | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_1G| MPU_RGN_ENABLE);

    NVIC_MPU_NUMBER_R = 3;
    NVIC_MPU_BASE_R = SRAM_BASE_ADD_1;
    NVIC_MPU_ATTR_R = ( MPU_RGN_PERM_NOEXEC | MPU_RGN_PERM_PRV_RW_USR_RW |SRAM_TEX_S_C_B
                | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_16K | MPU_RGN_ENABLE);

   /* NVIC_MPU_NUMBER_R = 4;
    NVIC_MPU_BASE_R = SRAM_BASE_ADD_2;
    NVIC_MPU_ATTR_R = ( MPU_RGN_PERM_NOEXEC | MPU_RGN_PERM_PRV_RW_USR_RW |SRAM_TEX_S_C_B
                | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_16K | MPU_RGN_ENABLE);*/

    NVIC_MPU_NUMBER_R = 4;
       NVIC_MPU_BASE_R |= SRAM_BASE_ADD_2;
       NVIC_MPU_ATTR_R |= ( MPU_RGN_PERM_NOEXEC | MPU_RGN_PERM_PRV_RW_USR_RW |SRAM_TEX_S_C_B
                   | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_2K | MPU_RGN_ENABLE);

       NVIC_MPU_NUMBER_R = 5;
       NVIC_MPU_BASE_R |= 0x20004500;
       NVIC_MPU_ATTR_R |= ( MPU_RGN_PERM_NOEXEC | MPU_RGN_PERM_PRV_RW_USR_RW |SRAM_TEX_S_C_B
                      | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_2K | MPU_RGN_ENABLE);
       NVIC_MPU_NUMBER_R = 6;
       NVIC_MPU_BASE_R |= 0x20005000;
       NVIC_MPU_ATTR_R |= ( MPU_RGN_PERM_NOEXEC | MPU_RGN_PERM_PRV_RW_USR_RW |SRAM_TEX_S_C_B
                                | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_8K | MPU_RGN_ENABLE);

       NVIC_MPU_NUMBER_R = 7;
       NVIC_MPU_BASE_R = 0xE0000000;
       NVIC_MPU_ATTR_R = ( MPU_RGN_PERM_NOEXEC | MPU_RGN_PERM_PRV_RW_USR_NO |SRAM_TEX_S_C_B
                | MPU_SUB_RGN_ENABLE_ALL | MPU_RGN_SIZE_1M | MPU_RGN_ENABLE);


    NVIC_MPU_CTRL_R =  MPU_CONFIG_PRIV_DEFAULT  | MPU_RGN_ENABLE ;
    //__asm(" DSB");

}