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Calyx back-end issues #427

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@Mark1626

Description

@Mark1626

I noted these two issue when I was trying to add float support in Dahlia (Calyx backend)

1. Hoist memory pass issue

The following does not pass with --lower flag.

decl a: float[128];
decl b: bit<10>[128];
decl c: float[128];

for (let i:bit<8>=0..128) {
    c[i] := a[b[i]];
}

Error

[Type error] [Line 0, Column 0] `b_read0' is not bound in scope.
<undefined position>

Root cause seems to be the Hoist pass, b_read0 has not been created

===============Original===============
decl a: float[128];
decl b: bit<10>[128];
decl c: float[128];
for (let i: bit<8> = 0 .. 128) {
  c[i] := a[b[i]];
}
======================================
===============Hoist memory reads===============
decl a: float[128];
decl b: bit<10>[128];
decl c: float[128];
for (let i: bit<8> = 0 .. 128) {
  let a_read0 = a[b_read0];
  c[i] := a_read0;
}


2. Incorrect usage of signed Calyx primitives

The following generates Calyx IR

decl a: bit<10>[128];
decl b: bit<10>[128];
decl c: bit<10>[128];

for (let i:bit<8>=0..128) {
    c[i] := a[i] & b[i];
}

The Calyx IR contains a std_sand primitive which seems to be not present in the current Calyx primitives

import "primitives/core.futil";
import "primitives/memories/seq.futil";
import "primitives/binary_operators.futil";
import "P32.futil";
component main() -> () {
  cells {
    @external(1) a = seq_mem_d1(10,128,8);
    a_read0_0 = std_reg(10);
    add0 = std_sadd(8);
    and0 = std_sand(10);
   ...
   ...
   ...

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