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Idea 1: Records are lowered to separate variables
Currently the Lower unroll and bank
pass lowers arrays
let x: ubit<32>[64 bank 4];
after lowering
let x0: ubit<32>[16];
let x1: ubit<32>[16];
let x2: ubit<32>[16];
let x3: ubit<32>[16];
Similarly a record can be lowered
record ivector_t {
x: bit<32>;
y: bit<32>;
z: bit<32>
}
let arr : ivector_t[128];
to something like this
let arr_ivector_t_x : bit<32>[128];
let arr_ivector_t_y : bit<32>[128];
let arr_ivector_t_z : bit<32>[128];
Cons:
- This would also affect the Vivado/Vitis HLS backend (maybe a good thing?)
Idea 2: Calyx specific
- Given a record the bit-width can be determined as the sum of individual elems. This can be used to create a
std_reg
orseq_mem
of given width
Let me know your thoughts @rachitnigam
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