Question about IO current?

[Zepan]

Is it necessary to use two pins to share the current? Approximately how much current is required here?
If a single pin is used, CVBS output could fit within a single PMOD (8IO).
(I'm from SIPEED, we currently make TangConsole RetroGaming, maybe this project can offer CVBS output ability for it!)

[Slamy]

Hello. This project is now a long time ago for me and I don't remember everything.
The alternative top level module https://github.com/Slamy/fpga-composite-video/blob/main/rtl/top_dactest_sawtooth.sv was exactly there to fine tune this problem.
Under ideal conditions, it should show a sawtooth wave on a scope. This however was not achievable with a single bank of the TangNano 9k. The amount of current was not sufficient and there was a non linearity at 3 positions of the sawtooth wave. There was also a crosstalk between the pins.
To avoid this issue, I've split the amount of current.
I had plans for adding a high speed external DAC but never did that. It could also be possible to create the signal and amplify that with an opamp with higher resistor values to reduce to burded on the I/O of the FPGA. However, this was not the project goal for me as I wanted this to be as simple as possible for everyone to understand.
I'm sorry, this might not be the answer you were looking for.

Edit:Without an opamp, the resistor values could not have been increased as the voltage of the output will drop and not reach the required amount to actually show white on some monitors.

Edit2: I should note that there might be other approaches to this problem.
I don't know how the MiSTer project solved this but I do recall that it was also a R2R ladder network.
I also thought about a different solution with a sigma delta approach and a SERDES. This essentially would have resulted into a single pin solution. But I never tried that.